The present invention relates generally to silicon-on-insulator devices and more particularly to integration of partially and fully depleted silicon-on-insulator devices on a single wafer die.
Silicon-on-insulator (SOI) devices have often been dubbed as the next successor to the reigning complimentary metal-on-silicon (CMOS) field effect transistors (FET) devices. SOI device advantages include excellent isolation protection against cross-talk, almost null leakage, latch-up immunity, radiation hardness, reduced junction capacitance, and reduced junction leakage currents. In addition, fully depleted SOI devices offer additional advantages. They provide reduced short channel effect, near ideal sub-threshold slope, increased transconductance, and reduced threshold voltage (Vt) sensitivity to changes in body doping, channel length, temperature, and substrate voltage. Fully depleted SOI devices are those in which the layer of semiconductor is sufficiently thin that the entire thickness of the body region is depleted of majority carriers when in the off state and both diffusion junctions are at ground.
In some CMOS FET devices, n-channel MOS transistors are coupled to a complimentary p-channel MOS transistor to provide an integrated circuit having very low power requirements.
The capability of having both partially and fully depleted SOI devices on the same wafer die has not previously been possible. Further, the possibility of making either PMOS or NMOS devices of either the partially depleted or fully depleted SOI devices has also not previously been possible.
A system for integrating both partially depleted and fully depleted SOI devices and PMOS and NMOS devices within a single die has long been sought, but has long eluded those skilled in the art.
The present invention provides a silicon-on-insulator semiconductor device in which a single wafer die contains a transistor in a silicon island over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure to form partially depleted silicon-on-insulator devices.
The present invention further provides a manufacturing method for having both partially and fully depleted silicon-on-insulator field effect transistor devices on the same wafer die, and a system for integrating either PMOS or NMOS devices of either the partially depleted or fully depleted silicon-on-insulator field effect transistor devices within a single die by using conventional doping processes.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.